In general, two rectifying schemes are used in a flyback converter, non-synchronous rectification which requires a diode as seen in prior art FIG. 1A and synchronous rectification which rectifies the current through controlling on/off of a synchronous rectifier, e.g. an N-MOSFET M, as seen in prior art FIG. 1B. When a high voltage is applied to the gate of an N-MOSFET, a channel forms and the N-MOSFET is turned on with very low ON resistance. When the gate is floating or a low voltage is applied, the drain-source resistance of the MOSFET is high.
Prior art FIG. 1C shows the voltage-current characteristic for a diode (curve 12) and for a synchronous rectifier (curve 11). In practical application, the operational region of flyback power converter falls into the cross-hatched area where curve 11 is above curve 12. That is, the ON resistance of a synchronous rectifier is less than that of its body diode. Thus, synchronous rectification is widely used to save power.
However, during light load conditions, the power saved by the synchronous rectification is minor, and is even less than the power consumed by the synchronous rectification driver. For this reason, it is usual to “latch off” the synchronous rectification function to save the driver loss. For a synchronous rectifier, typically a MOSFET, the body diode is used during the non-synchronous rectification where the positive current flows through the body diode of the MOSFET, instead of the channel which appears only when the MOSFET is actuated during synchronous rectification.
A conventional synchronous rectification method and its light load control solution will be described according to FIG. 1B and prior art FIG. 2. Assume that the secondary rectifier M is under synchronous rectification. At time t0, the primary side switch P is on, the secondary rectifier M is off with low gate voltage VGS. At that time, the drain-source voltage VDS is positive and the body diode of the secondary rectifier M is reverse-biased. At time t1, the primary side switch is turned off, and then the secondary rectifier M is turned on entirely with high gate voltage, current flows from the source to the drain and VDS is negative. As time elapses, VGS remains constant high, and VDS increases. The lighter the load, the quicker the voltage VDS increases. After VDS becomes negative at time t1, a blanking time is added. At the end of the blanking time t2, the drain-source voltage VDS of the rectifier M is sensed and compared to a predetermined voltage such as “zero” voltage. If VDS>0, a light load condition is determined and synchronous rectification is latched off into non-synchronous rectification. Then, the rectifier M is turned off with low VGS. VGS keeps low (OFF state) for the following cycles.
During the non-synchronous rectification, after VDS changes from a positive value to a negative value, and another blanking time is added. At the end of the blanking time, VDS is compared with the predetermined value such as “zero” voltage. If VDS<0, heavy load condition is determined and synchronous rectification is active again.
However, when the load is at a “border” condition, system will shift frequently between the synchronous rectification and non-synchronous rectification. This situation lowers the efficiency of the system. The rectification mode changes based on only one cycle of light load condition, this is unreliable and is susceptible to signal spikes. Furthermore, during the light load condition, the current at the secondary side will become negative before the rectifier M is turned off, which also lowers efficiency.